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MITSUBISHI
M66290AGP/FP
Ver.1.0 Oct. 27, 2000
USB DEVICE CONTROLLER
DESCRIPTION
The M66290A is a general purpose USB (Univ ersal Serial Bus) dev ice controller compatible with the USB specif ication v ersion 1.1 and corresponds to f ull speed transf er. Built-in transceiv er circuits meet all transf er ty pe which is def ined in USB. M66290A has FIFO of 3k By tes f or data transf er and can set 6 endpoints (maximum). Each endpoint can be set programmable of its transf er condition, so can correspond to each dev ice class transf er sy stem of USB.
FEATURES
* * * * USB specif ication 1.1 compliant Built-in USB transceiv er circuit Supports Full Speed (12 Mbps) transmission Supports all f our USB transf er t y pe : * Control transf er * Bulk transf er * Isochronous transf er * Interrupt transf er * Built-in FIFO (3 KBy tes) f or Endpoint * Up to 6 endpoint (EP0 to EP5) selectable
* Data transf er condition selectable f or each Endpoints (EP1 to EP5) * Data transf er t y pe (Bulk, Isochronous and Interrupt) * Transf er direction (IN/OUT) * Buf f er size of FIFO (maximum 1024 By tes) * Double (Toggle) buf f er conf iguration * Continuous transf er mode (Buf f ering up to 1 KBy teX2) * Max packet size * Supports 4 input clock f requencies * Input clock : 6/12/24/48 MHz * Built-in PLL which has an oscillation buf f er and outputs at 48 MHz * Supports both 8-bit and 16-bit DMA transf ers * 16-bit CPU bus interf ace * 3.3V single power source * Built-in JTAG
APPLICATION
* Printer , Scanner , DSC , DVC * PC camera , Multimedia speaker , Terminal adapter etc. * Support all PC peripheral using Full Speed USB
PIN CONFIGURATION (TOP VIEW)
DATA BUS
TEST2 INPUT INTERRUPT READ STROBE WRITE STROBE CHIP SELECT RESET DMA REQUEST DMA ACKNOWLEDGE
D12 D13 D14 D15 TEST2 INT RD WR CS RST Dreq Dack
37 38 39 40 41 42 43 44 45 46 47 48
24 23 22 21
M66290AGP OR M66290AFP
20 19 18 17 16 15 14 13
D1 D0 A6 A5 A4 A3 A2 A1 VCC GND Xin Xout
DATA BUS
ADDRESS BUS
OSCILLAT OR INPUT OSCILLAT OR OUTPUT
Outline
M66290AGP:48P6Q-A(LQFP) M66290AFP:48P6X-A(TQFP)
c MITSUBISHI ELECTRIC CORPORATION
1
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
VCC
1 16 35
BLOCK DIAGRAM
Xin Xout
14 13
Clock Control (Oscillator/ PLL)
17
to
A6 to 1
22
Vbus T rON
5 6
USB Peripheral Circuit
Device Control Unit
23
to
D15 to 0
40 45
CS WR RD INT
Serial Interface Engine
CPU Register
44 43
68 42
D+ D-
4 3
USB Transceiver
TRST TCK T MS TDI TDO TEST1 TEST2
8 9 10 11 12 7 41 2 15 36
Endpoint Buffer (3KByte FIFO)
47
68 48
Dreq Dack
46
RST
GND
BLOCK DESCRIPTIONS
The M66290A contains USB transceiv er, oscillation circuit, PLL, serial interf ace engine, endpoint buf f er, dev ice control unit, and CPU register. USB Transceiv er USB Transceiv er is consisted of dif f erential driv er and dif f erential receiv er. And is compatible with USB specif ication v ersion 1.1 and corresponds to Full Speed Transf er mode. Serial Interf ace Engine (SIE) SIE handles protocol lay er as f ollows. Extract a USB 12MHz clock Serial-Parallel data conv ersion SYNC detection NRZI encode and decode Bit stuf f ing and destuf f ing CRC generator and checker Dev ice Control Unit (DCU) DCU controls the dev ice state sequence, control transf er sequence, and so on. Endpoint Buf f er This is a FIFO buf f er f or transmit and receiv e between endpoints. Except f or EP0 f or control transf er, f iv e endpoints (EP1 to EP5) can be set. CPU Register This is an interf ace block with CPU. Oscillator/PLL This block oscillates the internal operation clock source of 48MHz. External clock of 6/12/24/48MHz can be input. USB peripheral circuit Detect the connection and the shutdown of USB by the Vbus input. Connect the Vbus of U SB bus to or the 5V power supply to Vbus input. Connect the TrON output to D+ pull-up resistor of 1.5kohm. ON/OFF of the pull-up resistor is controlled by the register.
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MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
PIN DESCRIPTIONS
Item Pin name Input/ D15 to D0 A6 to A1 CS CPU interface WR RD INT Dreq DMA interface Dack D+ DUSB interface Vbus Input Input Input Output Output Function
Number of
Input/ DATA BUS Output Data bus to access the register from the system Input Input ADDRESS BUS Address bus to access the register from the system CHIP SELECT "L" level enables to communicate with M66290A WRITE STROBE Input data is written into the register by the positive edge READ STROBE Register data can be read when "L" level INTERRUPT "L" level requests interrupt to system DMA REQUEST DMA transfer request to endpoint FIFO DMA ACKNOWLEDGE FIFO access by DMA transfer is available in "L" level
16 6 1 1 1 1 1 1 1 1
Input/ USB DATA(+) Output D+ of USB. Connect the external resistor serially. Input/ USB DATA(-) Output D- of USB. Connect the external resistor serially. Input Vbus INPUT (Built-in pull down resistor) Connect to the Vbus of USB bus or to the 5V power supply. Connection or shutdown of the Vbus can be detected.
1
TrON
TrON OUTPUT Output Connect to the D+ pull-up resistor of 1.5kohm. ON/OFF control of the pull-up resistor is available. Input TEST RESET INPUT (Built-in pull up resistor) Reset input of JTAG. Even if the JTAG is not used, JTAG circuit must be initialized. Input "L" level to initialize like the RST input. TEST MODE INPUT (Built-in pull up resistor) Mode set input to JTAG. If JTAG is not used, keep "H" level or open. TEST CLOCK INPUT (Built-in pull down resistor) Clock input to JTAG. If JTAG is not used, keep "L" level or open. TEST DATA INPUT (Built-in pull up resistor) Data input to JTAG. If JTAG is not used, keep "H" level or open. TEST DATA OUTPUT Data output from JTAG. If the JTAG is not used, keep open. RESET "L" level initializes the register or the counter of M66290A.
1
TRST
1
TMS JTAG interface TCK
Input Input
1 1 1 1 1 1 1 1 1
3 3
TDI TDO RST Xin Xout Others TEST1 TEST2 VCC GND
Input Output Input Input
OSCILLATO Generate an internal clock. R INPUT Input or output of internal clock oscillator. When use as a crystal oscillator, connect a OSCILLATO crystal between Xin and Xout. Output R OUTPUT If an external clock is used, input it to Xin, and Xout must be opened. Input Input TEST1 INPUT (Built-in pull down resistor) Input for the test. Keep "L" level or open. TEST2 INPUT (Built-in pull down resistor) Input for the test. Keep "L" level or open. Power supply pin Ground
-
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MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER USB DATA TRANSFER DESCRIPTIONS
M66290A is a USB dev ice controller correspond to all the f our ty pes of transf er (control, bulk, isochronous, and interrupt transf er), which is compatible to USB specif ication 1.1. M66290A acts USB f unctions as below automatically . (1) Bit stuf f ing/destuf f ing (2) CRC generate/check (3) NRZI encode/decode (4) Packet handling (5) USB address check (6) Bus error handling Theref ore, when CPU transact the operations as f ollows, USB transf er is realized. (1) Response to the control transf er request (2) Permission of store and transmission of the transmit data into the endpoint buf f er. (Or read of the receiv ed data f rom the endpoint buf f er) (3) Stall handling (4) Suspend/resume handling Below are the descriptions about the data transf er. Data receiv e In data receiv e, there are dif f erences of its f unction between setup transaction and out transaction. In setup transaction, when receiv ed dev ice request f rom host, 8By te request is alway s stored into f our resistors. When request data is receiv ed correctly ,sends back ACK packet to host and at the same time, occurs interrupt to CPU and urge CPU to read request. In out transaction, af ter M66290A receiv ed OUT token packet, host transmits data packet. If packet of m aximum packet size or short packet is stored into the endpoint FIFO of M66290A, and moreov er, error is not occurred in that transf er, M66290A transmits ACK packet to host and inf orms CPU that the data was receiv ed by occurring buf f er ready interrupt. If U SB protocol error is occurred in the host data which receiv ed v ia USB bus, or if the endpoint FIFO is f ull, M66290A does not transmit ACK packet to host. Host knows that the error occurred because the ACK packet does not come, and take a step such as data resend. 4 Data transmit When the data of endpoint FIFO, which corresponds to transmit request by IN token packet, is ready , M66290A transmit the corresponded data packet to USB bus. If the ACK packet come f rom the host f or the transmitted data packet, a transaction completed and the endpoint FIFO becomes empty and urge CPU to write the next transmit data by buf f er ready interrupt. If the transmit data, which correspond to transmit request by IN token packet, is not exist in the endpoint FIFO, M66290A transmit NAK packet to host when receiv ed IN token packet f rom host and occurs interrupt and request CPU to write transmit data. When M66290A receiv ed IN token packet again f rom host, M66290A transmits the data which is written. If error is not occurred in that transf er, host transmit ACK packet and if M66290A receiv ed it normally , a transaction completed. If U SB protocol error is occurred in the data which is transmitted v ia USB bus, host does not transmit ACK packet, so M66290A watch and wait until receiv e IN token packet, with keeping the data to be transmitted.
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER CONTROL REGISTER TABLE
Below is the table of registers of M66290A. Bit width of all register is 16bits. In reset item, "H/W" shows the reset status by external RST input, "S/W" shows reset status by USBE register, and "USB"
Address 00h 02h 04h 06h 08h 0Ah 0Ch to 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h to 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh to 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h Name USB Operation Enable Register Remote Wake-up Register Sequence Bit Clear Register Reserved USB_Address Register IsochronousStatus Register Reserved Interrupt Enable Register0 Interrupt Enable Register1 Interrupt Enable Register2 Interrupt Enable Register3 Interrupt Status Register0 Interrupt Status Register1 Interrupt Status Register2 Interrupt Status Register3 Request Register Value Register Index Register Length Register Control Transfer Control Register EP0 Packet Size Register Auto-response Control Register Reserved EP0_FIFO Selection Register EP0_FIFO Control Register EP0_FIFO Data Register EP0 Continuous transmit Data Length Reserved CPU_FIFO Selection Register CPU_FIFO Control Register CPU_FIFO Data Register Reserved DMA_FIFO Selection Register DMA_FIFO Control Register DMA_FIFO Data Register Reserved EP1 Configuration Register0 EP1 Configuration Register1 EP2 Configuration Register0 EP2 Configuration Register1 EP3 Configuration Register0 EP3 Configuration Register1 EP4 Configuration Register0 EP4 Configuration Register1 EP5 Configuration Register0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000h 0040h 0000h 0040h 0000h 0040h 0000h 0040h 0000h R/W R/W (note 2) R/W 0000h 0800h xxxx R/W R/W (note 2) R/W 0000h 0800h xxxx R/W R/W (note 2) R/W R/W 0000h 0800h xxxx 0000h R/W R/W R/W R/W R/W (note 2) R R/W R/W R R R R R/W R/W R/W 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0008h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Note 2 R R/W (note 2) 0000h 0000h 0000h 0000h 0000h -
shows the reset status by receiv ing USB reset. " - " shows that the prev ious status is kept. Write into reserv ed address is inhibited.
R/W R/W R/W R/W
H/W
S/W
USB
0000h 0000h 0000h
0000h 0000h
-
note 1 : Detail description is mentioned later. note 2 : Some are read only.
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MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER Functional and register descriptions
We explain about Function and register constitution of M66290A div iding into f our items as f ollows. (1) Sy stem control (2) Interrupts (3) Control transf er/enumeration (4) Endpoints and FIFO control And when use this f unction, dev ice state shif ts to Address state af ter outputs remote wakeup signal, so it is needed to set up again the dev ice state to Conf igured state. Change of set up of dev ice state can be done in S/W control mode. Remote wakeup signal is a signal to set USB bus to idle state af ter output K-state of 10ms length. If this remote wakeup f unction is set up immediately af ter detected suspend, USB bus idle state is kept f or 2ms and then shif ts to K state output. (Because USB bus idle state must be kept f or 5ms minimum until transmit of remote wakeup signal, on the other hand af ter detect suspend, USB idle state is continued f or 3ms) Sequence toggle bit clear f unction In each endpoint of EP0 to EP5, data PID can be reset independently and also can appoint PID of DATA0. By this f unction, management of sequence toggle bit in transf er af ter reset PID, is done by H/W automatically . Error inf ormation in isochronous transf er In isochronous transf er there is not retry f unction of transmit/receiv e, because the handshake f rom receiv er to transmitter is not returned not to disturb the time equiv alent data transf er. M66290A has enough inf ormation f unction which enables f irmware to manage incorrect transf er in case of transf er error occurred in isochronous transf er. Inf ormation which M66290A can inf orm is, ov er run error, under run error, receiv ed data error (CRC error, bit stuf f ing error), and f rame number. Sof tware control mode In sof tware control mode, it is av ailable to set up (write) f rom CPU as f ollows, USB_Address register (USB_Addr), dev ice state register (DVSQ), control transf er stage register (CTSQ). Normally , use this mode with OFF. (1) In case of crystal oscillation C1 Xin XTAL Rf M66290A Xout C2 Rd
Place the parts as near the terminal as possible
(1) System control
CLOCK Clock of 48MHz is needed f or internal operations of M66290A. Built in PLL enables to input external clock of 6/12/ 24/48MHz. Selection of it is realized by the XTAL of "USB Operation Enable Register". When use external clock of 48MHz, PLL is not needed, so set to PLL operation disable. Built in oscillation circuit enables to supply clock by self oscillation. To set the "USB Operation Enable Register", it can be set the dev ice to standby state. Oscillation is halted (clock input halted) by XCKE, PLL operation is halted by PLLC, and clock supply to USB block is halted by SCKE. To prev ent unstable behav ior by unstable clock, clock supply to USB block must be obey ed the process, that is, enables clock input by XCKE, wait until oscillation stabilized, start PLL by PLLC, wait until oscillation stabilized (less than 1ms), and start clock supply to USB block by SCKE. RESET S/W reset by the register set (USBE), dif f erent f rom the hardware reset, keeps the v alue of register of USB operation enable register, FIFO relational register, control transf er relational register,endpoint setting register, and so on. And in USB reset (when more than 2.5us of SE0 state is continued on D+, D- terminal), the v alue of register is kept except f or "Interrupt Status Register 0" and "USB_Address Register" As to details of reset state, see each item of register. D+ pull-up resistor control f unction To set the register, external TrON output is controlled and can control the ON/OFF of pull-up resistor (1.5kohm) on USB D+ line. Remote wakeup f unction When dev ice is in suspended state, outputs remote wakeup signal and can cancel suspended state to receiv e resume f rom USB. Remote wakeup f unction is only ef f ectiv e in Suspended state in which dev ice state shif ts f rom Conf igured state, so don't use to other dev ice state.
(2) In case of external clock input clock input Xin M66290A open Xout
Figure 1. Xin and Xout connections
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MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (1-1) USB Operation Enable Register (Address : 00h)
D15 XCKE D14 PLLC Bit Name XCKE D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 SCTR Reset Name Function 0 : Oscillator disable (clock input disable) 1 : Oscillator enable (clock input enable) 0 : PLL disable 1 : PLL enable When use external clock of 48MHz, set to PLL disable. 00 : 1/1 division (external 48MHz input) 10 : 1/2 division (external 24MHz input) 01 : 1/4 division (external 12MHz input) 11 : 1/8 division (external 6MHz input) 0 : Internal clock (sck) disable 1 : Internal clock (sck) enable 0 : USB transceiver disable 1 : USB transceiver enable In suspend state, resume signal can be received even if USB transceiver disabled. X0 : TrON port ="Hi-Z" 01 : TrON port ="L" 11 : TrON port ="H" This fields selects TrON output state, and it is effective when external Vbus input is "H" level (5V). If external Vbus input is "L", these bits can be set but TrON output does not operate. Write/Read "0" Software control mode USB module enable 0 : Normal Operation 1 : Software Control Mode Operation 0 : USB module disable (S/W Reset) 1 : USB module enable W/R 0 W/R H/W S/W USB Oscillator enable W/R 0 D0 USBE
XTAL[1:0]
SCKE USBPC
Tr_on[1:0]
Bit
15
14
PLLC
PLL control
W/R
0
-
-
13, 12 XTAL[1:0]
Crystal select
W/R
00
-
-
11
SCKE
Internal clock enable
W/R
0
-
-
10
USBPC
USB transceiver power control
W/R
0
-
-
9, 8
Tr_on [1:0]
Tr_on output control
W/R
00
-
-
7 to 2 Reserved 1 SCTR
0
USBE
W/R
0
-
-
(1-2) Remote Wake-up Register (Address : 02h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WKUP Bit Bit Name Name Write/Read "0" When CPU write "1" to WKUP for remote wake-up, M66290A outputs K-State for 10ms, and return to Bus Idle-State. (Remote wake-up signal) This bit returns to "0" automatically after suspend is canceled. If "1" is written into this bit after detected suspend, bus idle state is kept for 2ms and after then shifts to K state output. Function W/R Reset H/W S/W USB
15 to 1 Reserved
0
WKUP
Remote wake-up
W/R
0
0
-
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MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (1-3) Sequence Bit Clear Register (Address : 04h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SQCLR[5:0] Bit Name Reset H/W S/W USB
Bit
Name Write/Read "0"
Function
W/R
15 to 6 Reserved
5 to 0
When write "1" into the bit which is correspond to the number of endpoint, sequence toggle bit of that endpoint is cleared and appoint the DATA0 by the data PID of next transmission. Write "1" into the bit after set the response PID of the endpoint, which SQCLR Sequence toggle bit clears sequence toggle bit, to NAK("00") . Transfers After the transfer appointed, sequence toggle bit is controlled [5:0] clear by H/W. In USB reset, Sequence toggle bit of each endpoint is not cleared. If "0" is written into this bit, flag is not changed. Read data of this bit is always "0".
W/R
00h
00h
-
(1-4)USB Address Register (Address : 08h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
USB_Addr[6:0] Bit Name Reset H/W S/W USB
Bit
Name Write/Read "0"
Function
W/R
15 to 7 Reserved
6 to 0
USB_ Addr [6:0]
USB_Address register
USB address which is assigned by host is stored. After stored the address, transaction is done only to the token packet which is transmitted to this address. (If S/W control mode is set, write operation is available)
R
00h
00h 00h
8
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (1-5) Isochronous Status Register (Address : 0Ah)
D15 D14 D13 D12 D11 FMOD D10 D9 D8 D7 D6 D5 FRNM[10:0] D4 D3 D2 D1 D0
OVRN CRCE
Bit
Bit Name
Reset Name Function W/R H/W S/W USB
15
OVRN
Over run error
In isochronous transfers (OUT/IN), when over-run or under-run is occurred to the endpoint buffer, this flag is set at the timing of the receive end of the OUT/IN token packet. Over run is occurred when delayed to read the received data from the endpoint buffer, and means that could not received. Over run is occurred when the direction of transmission is OUT. Also the received data has CRC or bit stuffing error, this flag is set. Under run is occurred when delayed to write the transmit data into the endpoint buffer, and means that could not transmitted. Under-run is occurred when the direction of transmission is IN. When a state above is occurred, endpoint buffer notready interrupt is occurred. When "0" is written, status flag is cleared. When "1" is written, flag is not changed.
W/R
0
0
-
In isochronous transfers(OUT), if the received data has CRC or bit stuffing error, this flag is set at the timing of the end of transaction. When a state above is occurred, endpoint buffer notready interrupt is occurred. When "0" is written, status flag is cleared. When "1" is written, flag is not changed.
14
CRCE
Receive data error
W/R
0
0
-
13 to 12 Reserved
Write/Read "0" Select the renewal timing of the flame number to be stored to FRNM[10:0].
11
FMOD
Frame number mode
0 : Renew the flame number when SOF is received . 1 : In isochronous transfer, renew the flame number at the timing of the end of transaction.
W/R
0
0
-
10 to 0
FRNM [10:0]
Frame number
Stores the flame number. The timing to renew the stored flame number is selectable by set FMOD.
R
000h 000h
-
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MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (2) Interrupts
There are eight f actors of interrupt to CPU. When interrupt occurred, the f actor can be known to ref er to "Interrupt Status Register 0" and "Interrupt Status Register 1". These interrupts can be set of its enable/disable independently to set "Interrupt Enable Register 0" and "Interrupt Enable Register 1". If disable is set, interrupt is not occurred but interrupt status f lag is set. Each f actor of interrupt is shown in the table below, and also describes below the interrupt conditions and how to deal with the interrupt.
Resume detect interrupt (RESM)
If dev ice state is in suspended state and resume interrupt enable f lag is set, interrupt occurs when USB bus state is changed ("J" to "K" or "SE0"). This interrupt can be occurred ev en if the internal clock(sck) is halted. To clear the status f lag, set the internal clock(sck) in operation and then write "0". If the internal clock(sck) is halted, status f lag can not be cleared.
SOF detect interrupt (SOFR)
Interrupt occurs when detect SOF.
Vbus (connect/shut down) interrupt (VBUS)
Interrupt occurs when Vbus input state is changed (both "L" to "H" and "H" to "L"). To know Vbus input state, conf irm the Vbus bit of interrupt status register 0. Conf irmation of Vbus bit must be done af ter enabled internal clock operation. This interrupt can be occurred ev en if the internal clock(sck) is halted. To clear the status f lag, enables the internal clock(sck) in operation and then write "0". If the internal clock(sck) is halted, status f lag can not be cleared. This interrupt is usef ul to detect connect/shut-down of USB f or prepareration/close of USB transf ers.
Device state transition interrupt (DVST)
M66290A manages the dev ice state by H/W. It manages Powered, Def ault, Address, Conf igured, and Suspended state. Dev ice state can be known to ref er to "Interrupt Status Register 0". As to dev ice state shif t, see the item of "Dev ice state shif t" in "(3) Control transf er/emulation" in the latter part. Dev ice state transition interrupt occurs when dev ice state shif ted. The number of f actors is f our, that is, USB bus reset detect, suspend detect, execution of "Set Address", and execution of "Set Conf iguration". USB reset is detected when SE0 state ov er 2.5us is continued on D+, D- terminal. Suspend is detected when idle state ov er 3ms is continued on D+, D- terminal.
Summary of interrupts
Status bit VBUS RESM SOFR DVST CTRT Name Vbus interrupt (connec/shut-down detect) Resume detect interrupt SOF detect interrupt dev ice state transition interrupt Control transf er stage transition interrupt Endpoint buf f er empty /size-ov er interrupt Endpoint buf f er not ready interrupt Endpoint buf f er ready interrupt Abstract of interrupt f actor Change of the Vbus input (both "L" to "H" and "H" to "L") Resume signal receiv ed in suspended Receiv ed SOF Shif t of dev ice state Stage shif t of control transf er In each endpoint, when data transmit of all buf f er is ended and buf f er is empty , or in OUT transf er, receiv ed packet which exceeds max packet size. When buf f er is in not ready state (SIE cannot read and write) to IN/OUT token of each endpoint. When buf f er of each endpoint became ready (read enable/write enable) DVSQ[2:0] CTSQ[2:0] Relational status bit Vbus
BEMP
EPB_EMP_OVR[5:0]
INTN INTR
EPB_NRDY [5:0] EPB_RDY [5:0]
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MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
Each of "Set Address" and "Set Conf iguration" execution detects the dev ice state shif t by analy zing the dev ice request in control transf er. Each of these f our f actors can be set of its interrupt to enable or disable by setting the corresponded bit of interrupt enable register 0. For example by using this interrupt, when USB bus reset is detected, a step to USB bus is av ailable and when suspend is detected, a step to shif t dev ice to low power consumption.
Endpoint buffer not ready interrupt (INTN)
When the buf f er is in not ready state to IN/OUT token of each endpoint, interrupt occurs at the timing of token packet receiv e end. By ref er to EPB_NRDY[5:0] of interrupt status register 1, it can be known which endpoint occurred the interrupt. If endpoint is set to isochronous transf er, when ov er-run/ under-run error is occurred, interrupt occurs at the timing of token packet receiv e end. And if it is set to isochronous (OUT), if receiv ed data has error such as CRC error, interrupt occurs at the timing of transaction end. The v ariety of error in isochronous transf er is known to ref er "Isochronous Status Register".
Control transfer stage transition interrupt (CTRT)
M66290A manages the sequence of control transf er by H/W. Each stage of c ontrol transf er, such as setup stage, data stage, and status stage can be known to ref er to the "Interrupt Status Register 0". Control transf er stage transition interrupt is occurred when the control transf er stage is shif ted. There are f iv e f actors, that is, setup stage end, control write transf er stage shif t, control read transf er stage shif t, control transf er end, and control transf er sequence error. Except f or setup stage, Each of these f our f actors can be set of its interrupt to enable or disable by setting the corresponded bit of interrupt enable register 0. As to control transf er sequence error which can be recognized by H/W, ref er to "Control transf er stage shif t" in the item of "(3) Control transf er/enumeration" in the latter part.
Endpoint buffer ready interrupt (INTR)
Interrupt occurs when the buf f er of each endpoint became ready (read/write is av ailable). It can be known which endpoint occurred the interrupt to ref er EPB_RDY [5:0] of interrupt status register 1. According to the endpoint and its access mode, the f actor of interrupt is dif f erent as f ollows. 1. In case of EP0 Interrupt occurs when receiv e (OUT) buf f er of endpoint 0 became ready . If it is set to control write continuous receiv e mode, when continuous receiv e of 255 by tes ended or when receiv ed short packet, interrupt occurs. Interrupt is not occurred ev en if the transmit buf f er became ready . 2. In case of EP1 to EP5, when CPU access Interrupt occurs when the buf f er of each endpoint became ready . 3. In case of EP1 to EP5, when DMA access If the transf er direction is set to OUT, interrupt occurs when receiv ed short data packet and then ended DMA transf er. Interrupt is not occurred if the transf er direction is set to IN.
Endpoint buffer empty/size-over interrupt (BEMP)
Interrupt f actor is dif f erent by transf er direction of endpoint. 1. In case of transf er direction is IN In each endpoint, interrupt occurs when transmission ended of all data which is stored in the buf f er. By this interrupt, when endpoint is set to double buf f er, end of data transmission of all data of the buf f er can be known. And also can know the end of data transmission of control read transf er in endpoint 0 (EP0). 2. In case of transf er direction is OUT In each endpoint, interrupt occurs in data packet receiv e when receiv ed packet which exceeds the maximum packet size. By ref er to EPB_EMP_OVR[5:0] of interrupt status register, it can be known which endpoint occurred the interrupt.
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MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
Figure 2. shows the examples of interrupt output timing
(1) Endpoint buf f er ready interrupt (ex.OUT transaction) OUT token packet USB
SYNC PID Addr Endp CRC EOP
Data packet
SYNC PID DATA CRC EOP
Hand shake packet (ACK)
SYNC PID EOP
INT output
Buf f er becomes ready (read enable) and interrupt occurs
(2) Endpoint buf f er not ready interrupt (ex.OUT transaction) OUT token packet USB
SYNC PID Addr Endp CRC EOP
Data packet
SYNC PID DATA CRC EOP
Hand shake packet (NAK)
SYNC PID EOP
INT output
Buf f er is in not ready (receiv e disable) and interrupt occurs
(3) Endpoint buf f er not ready interrupt (ex.IN transaction) IN token packet USB
SYNC PID Addr Endp CRC EOP
Hand shake packet (NAK)
SYNC PID EOP
INT output
Buf f er is in not ready (transmit disable) and interrupt occurs
Figure 2. Examples of interrupt output timing
12
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(2-1) Interrupt Enable Register 0 (Address : 10h)
D15 D14 D13 D12 DVSE D11 D10 D9 D8 D7 D6 D5 D4 SUSP D3 D2 D1 D0
VBSE RSME SOFE Bit Name VBSE RSME
CTRE BEMPE INTNE INTRE URST
SADR SCFG
WDST RDST
CMPL SERR Reset H/W S/W USB 0 0 0 0 -
Bit 15 14
Name Vbus interrupt enable Resume interrupt enable SOF interrupt enable Device state interrupt enable Control transfer interrupt enable Endpoint5-0 buffer empty/size error interrupt enable Endpoint5-0 buffer not ready interrupt enable Endpoint5-0 buffer ready interrupt enable USB reset detect Set Address execute Set Configration execute Suspend detect Control write transfer status stage Control read transfer status stage Control transfer complete 0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 : Disable 1 : Enable
Function
W/R W/R W/R
13
SOFE
W/R
0
0
-
12
DVSE
W/R
0
0
-
11
CTRE
W/R
0
0
-
10
BEMPE
W/R
0
0
-
9
INTNE
0 : Disable 1 : Enable
W/R
0
0
-
8
INTRE
0 : Disable 1 : Enable
W/R
0
0
-
7
URST
If this bit is "1", then the DVST flag is set when detected USB reset.
W/R
0
0
-
6
SADR
If this bit is "1", then the DVST flag is set after executed SetAddress.
W/R
0
0
-
5
SCFG
If this bit is "1", then the DVST flag is set after executed SetConfigration.
W/R
0
0
-
4
SUSP
If this bit is "1", then the DVST flag is set when detected suspend.
W/R
0
0
-
3
WDST
If this bit is "1", then the CTRT flag is set when shifted to status stage in control write transfer.
W/R
0
0
-
2
RDST
If this bit is "1", then the CTRT flag is set when shifted to status stage in control read transfer.
W/R
0
0
-
1
CMPL
If this bit is "1", then the CTRT flag is set when control transfer completed (when the status stage completed normally).
W/R
0
0
-
0
SERR
Control transfer sequence error
If this bit is "1" then the CTRT flag is set when error occurred in the sequence of control transfer.
W/R
0
0
-
13
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (2-2) Interrupt Enable Register 1(Address : 12h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EPB_RE[5:0] Bit Name Reset H/W S/W USB
Bit
Name Write/Read "0" Endpoint5-0 buffer ready interrupt enable
Function
W/R
15 to 6 Reserved EPB_RE [5:0]
5 to 0
0 : Disable 1 : Enable The number of endpoint is correspond to each bit one by one.
W/R
00h
00h
-
(2-3) Interrupt Enable Register 2 (Address : 14h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EPB_NRE[5:0] Bit Bit Name Name Write/Read "0" Endpoint5-0 buffer not ready interrupt enable 0 : Disable 1 : Enable The number of endpoint is correspond to each bit one by one. Function W/R Reset H/W S/W USB
15 to 6 Reserved EPB_NRE [5:0]
5 to 0
W/R
00h
00h
-
(2-4) Interrupt Enable Register 3 (Address : 16h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EPB_EMPE[5:0] Bit Name Reset H/W S/W USB
Bit
Name Write/Read "0" Endpoint5-0 buffer empty/size error interrupt enable
Function
W/R
15 to 6 Reserved EPB_ EMPE [5:0]
5 to 0
0 : Disable 1 : Enable The number of endpoint is correspond to each bit one by one.
W/R
00h
00h
-
14
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(2-5) Interrupt Status Register 0 (Address : 18h)
D15 D14 D13 SOFR D12 DVST D11 CTRT D10 BEMP D9 INTN D8 INTR D7 Vbus D6 D5 DVSQ[2:0] D4 D3 VALID D2 D1 CTSQ[2:0] Reset H/W S/W USB D0
VBUS RESM Bit Name
Bit
Name
Function
W/R
15
VBUS
Vbus interrupt
This bit changes to "1" when Vbus input changed both "0" to "1" and "1" to "0". As to the Vbus input state, confirm to see the bit of Vbus input port. This bit is set even if the internal clock (sck) is in halt state. If "0" is written after enabled internal clock as operation, status flag is cleared. But if internal clock is in halt state, flag is not cleared. If "1" is written, flag is not changed.
W/R
0
0
-
14
RESM
Resume detect interrupt
This bit changes to "1" when USB bus state changed("J" to "K" or "SE0") under the condition that resume interrupt enable flag is set. This bit is set even if the internal clock (sck) is in halt state. If "0" is written after enabled internal clock as operation, status flag is cleared. But if internal clock is in halt state, flag is not cleared. If "1" is written, flag is not changed.
W/R
0
0
-
13
SOFR
SOF detect interrupt
This bit changes to "1" when detected SOF. If "0" is written, status flag is cleared. If "1" is written, flag is not changed.
W/R
0
0
-
12
DVST
This bit changes to "1" when device state shifted. There are four factors, that is, USB reset detect, suspend detect, "Set Address" execution, and "Set Configuration" execution. Device state These four factors can be masked by the corresponded bit of transition interrupt "Interrupt Enable Register0" . If "0" is written, status flag is cleared. If "1" is written, flag is not changed.
W/R
0
0
1
11
CTRT
Control transfer stage transition interrupt
This bit changes to "1" when the stage of control transfer is shifted. There are five factors, that is, setup stage end, control write transfer status stage shift, control read transfer status stage shift, control transfer end, and control transfer sequence error. Four factors, except for setup stage end, can be masked by the corresponded bit of the "Interrupt Enable Register0". If "0" is written, status flag is cleared. If "1" is written, flag is not changed.
W/R
0
0
-
10
BEMP
The factor is different by the direction of the transfer of each endpoint. In each endpoint, this bit changes to "1" when the transmission of all stored data is completed (direction:IN) and when received the packet Endpoint5-0 buffer which is exceeded to maximum packet size (direction:OUT). The endpoint which occurs the interrupt can be checked to see the empty/size error interrupt EPB_EMP_OVR[5:0]. This flag is cleared to clear the status flag of EPB_EMP_OVR[5:0].
R
0
0
-
15
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
Bit Name
Name
Function
W/R
Reset H/W S/W USB
9
INTN
This bit changes to "1" at the timing of token packet receive end when buffer respond NAK, of its not ready state, to IN/OUT token of each Endpoint5-0 buffer endpoint. not ready The endpoint which occurred the interrupt is checked to see interrupt enable EPB_NRDY[5:0]. This flag is cleared to clear the status flag of EPB_NRDY[5:0]. This bit changes to "1" when the buffer of each endpoint became ready (read/write enable).
R
0
0
-
8
INTR
Endpoint5-0 buffer ready interrupt enable
The endpoint which occurred the interrupt is checked to see EPB_RDY[5:0]. This flag is cleared to clear the status flag of EPB_RDY[5:0].
R
0
0
-
7
Vbus
Vbus input port
Input data from external Vbus is stored. 0: Vbus input port is "L" 1: Vbus input port is "H" External Vbus input data is latched by the positive edge of internal clock. Refer to this bit after enabled internal clock operation. 000: Powered State 001: Default State 010: Address State 011: Configured State 1xx: Suspended State Device state can be known. As to the device state shift, refer to Fig.5 in the later part. When detect USB reset, this becomes 001: Default state automatically. When detect suspend, this becomes 1xx: Suspended state automatically. Whatever the automatic response mode is, this becomes 010: Address state after executed Set_Address request, and becomes 011: Configured state after executed Set_Configuration request. (Write operation is available when S/W control mode is set)
R
Ext.
Ext. Ext.
6-4
DVSQ [2:0]
Device state
R
000
000 001
3
VALID
Setup packet detect
This bit changes to "1" when received setup packet. This flag does not the factor of interrupt. When "0" is written, status flag is cleared . When "1" is written, flag is not changed . 000 : Idle or Setup stage 001 : Control read transfer data stage 010 : Control read transfer status stage 011 : Control write transfer data stage 100 : Control write transfer status stage 101 : Control write no data transfer status stage 110 : Control transfer sequence error 111 : Not assigned Can be seen the stage of control transfer. As to the stage shift of control transfer, refer to Fig.5 in the later part. (Write operation is available when S/W control mode is set)
W/R
0
0
-
2-0
CTSQ [2:0]
Control transfer Stage
R
000
000
-
16
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (2-6) Interrupt Status Register 1 (Address : 1Ah)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EPB_RDY[5:0] Bit Name Reset H/W S/W USB
Bit
Name Write/Read "0"
Function
W/R
15 to 6 Reserved
When buffer becomes ready (read/write enabled) to each endpoint, the bit which corresponds to the number of endpoint changes to "1". The factor of the interrupt is different by the transfer condition of each endpoint. 1. As to EP0 This bit changes to "1" when receive buffer(OUT) became ready (read enabled) in control write transfer. If it is set to control write continuous receive mode or completed receiving of the data of 255Bytes or received short data packet, this bit changes to "1". This bit is not changed even if the transmission buffer(IN) became ready (write enabled) in control read transfer. The ready state of the transmission buffer(IN) can be known by the buffer empty interrupt. 2. As to EP1 to EP5, when CPU access This bit changes to "1" when each buffer of each endpoint became ready(read/write enabled). This bit also changes to "1" when set the direction of the transfer to IN in initialization. R 3. As to EP1 to EP5, when DAM access If the direction of the transfer is set to OUT, this bit changes to "1" when received short data packet and then completed DMA transfer of received data. In this case, clear is only available to write the BCLR command. This bit is not changed if the direction of transfer is set to IN. Clearance of this flag is different by the transfer direction of endpoint. 1. If the transfer direction is OUT After set the number of the object endpoint to the "FIFO Selection Register", write BCLR command or read all data of the buffer, then flag is cleared. (When DMA access, clearance is only available to write BCLR command) 2. If the direction is IN After set the number of the object endpoint to the "FIFO Selection Register", write IVAL command or write data into the buffer of maximum packet size (buffer size, if in continuous transmission mode ), then flag is cleared. 00h 00h -
5 to 0
EPB_RDY [5:0]
Endpoint5-0 buffer ready interrupt
17
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(2-7) Interrupt Status Register 2 (Address : 1Ch)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EPB_NRDY[5:0] Bit Name Reset H/W S/W USB
Bit
Name Write/Read "0"
Function
W/R
15 to 6 Reserved
To IN/OUT token of each endpoint, if the set of response PID is not NAK("00") and if buffer is in not ready state (receive/transmit disabled), the bit which corresponds to the number of endpoint changes to "1". (If the endpoint is control transfer or bulk transfer or interrupt transfer, NAK response is executed) EPB_ NRDY [5:0] Endpoint5-0 buffer not ready interrupt If the endpoint is set to isochronous transfer, M66290A does not execute NAK response, but when over-run or under-run of endpoint buffer occurred, this bit changes to "1" at the timing of token packet receive end. If it is set to isochronous (OUT), and if received data has error such as CRC, this bit changes to "1" at the timing of transaction end. When "0" is written, status flag is cleared. When "1" is written, flag is not changed.
5 to 0
W/R
00h 00h
-
18
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(2-8) Interrupt Status Register 3 (Address : 1Eh)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EPB_EMP_OVR[5:0] Bit Name Reset H/W S/W USB
Bit
Name Write/Read "0"
Function
W/R
15 to 6 Reserved
When factors below are occurred to each endpoint, the bit which corresponds to the number of endpoint, changes to "1". 1. If the transfer direction is IN In each endpoint, when transmission completed of all data which stored in buffer, c By this interrupt, if endpoint is set to double buffer, it can be known that transmission of all data of buffer is completed. And also by this interrupt, it can be known that transmission of EP0 is completed. 2. If the direction is OUT In each endpoint, when received data which exceeds the maximum packet size in data packet receive, the bit which corresponds to the number of endpoint changes to "1".
5 to 0
EPB_ EMP_ OVR [5:0]
Endpoint5-0 buffer empty/size error interrupt
W/R
00h 00h
-
When "0" is written, status flag is cleared. When "1" is written, status flag is not cleared.
19
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (3) Control transfer / Enumeration
In control transf er, there are setup stage, data stage, and status stage. M66290A manages stage and inf orm CPU the stage shif t by interrupt. CPU do stage transact of control transf er according to the interrupt f actor. If it is control read transf er, data stage is IN transaction and CPU prepares f or data transmit (write into endpoint FIFO) at the timing of interrupt in setup stage. M66290A is equipped with control transf er continuous transmit and receiv e f unction. Af ter ended data stage, it proceeds to status stage.
Setup stage
In setup stage, 8By tes request (setup data) of setup transaction data packet which transf erred f rom host is stored into f our registers automatically (Request, Value, Index, and Length register). Except f or dev ice state shif t request (Set Address and Set Conf iguration) which can cope with by the automatic response control f unction, analy sis (decode) and execution of contents of request must be done by CPU. By executing the request, it proceeds to data stage or to status stage.
Status stage
Status stage executes receiv e/transmit of N ull data (data length 0), in both control write and control read transf er. Receiv e/transmit of N ull data is possible to set control transf er complete enable bit (CCPL) af ter ended setup stage. Control transf er complete enable bit is reset when receiv ed setup packet. Control transf er executes data transf er using EP0. To both control read and control write, buf f er size of EP0 can be set by a unit of 64By tes by "Control Transf er Control Register". Access to EP0_FIFO data register must be done by CPU access. DMA transf er can not be set. Figure 3. shows the abstract of enumeration operations.
Data stage
Data stage executes IN transaction or OUT transaction according to the contents of request. If it is control write transf er, data stage is OUT transaction and CPU prepares f or data receiv e at the timing of interrupt in setup stage and reads the receiv ed data f rom endpoint FIFO when data receiv e ended. M66290A
Dev ice f irmware Clock ON Initializing Tr ON
Dev ice state Idle (Powered)
USB bus connect Full speed dev ice recognition USB reset USB request (Control transf er)
Vbus interrupt
USB reset receiv e DVST interrupt Get xx command CTRT interrupt Set response data
Def ault state
USB request
Set Address CTRT/DVST interrupt (Automatic response av ailable) Get xx command CTRT interrupt Set response data
Address state
USB request
USB request
Set Conf iguration CTRT/DVST interrupt (Automatic response av ailable) Set xx command CTRT interrupt Read receiv ed data
Conf igured state
USB request
Figure 3. Abstract of enumeration operations
20
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER Auto-response control function
M66290A has auto-response f unction to dev ice state transition request (Set Address and Set Conf iguration)in control transf er. By the set of "Auto-response Control Register", auto-response mode to Set Address and to Set Conf iguration can be set indiv idually . If the auto-response mode is set, dev ice state transition request can be ended without occurring interrupt. which extend plural of transaction. If continuous transf er mode is set, it can transf er the transmit which data length is set to "EP0 Continuous Transmit Data Length Register", without occurring interrupt. Control read buf f er can be set up to 256By tes at a unit of 64By tes. Control write buf f er can receiv e continuously up to 255By tes, so secure the area of 256By tes.
Continuous transfer function
M66290A has continuous transf er f unction to transmit/receiv e continuously of requested data
Abstract of control transfer operations
Figure 4. shows examples of abstraction of control transf er operations. Host to M66290A M66290A to Host
Transf er direction of packet :
(1) Continuous receive mode (control write transfer)
Setup stage
INT1
Setup token OUT token OUT token
Data packet Data packet Data packet Data packet Data packet Data packet
INT2
ACK NAK NAK ACK ACK ACK
INT1: CTRT interrupt (setup stage completion) Read EP0 request and conf irm the contents of request. By receiv ing SETUP token packet, response PID of EP0 is set to NAK automatically . By the set of response PID to BUF (buf f er control), data receiv e starts.
Data stage
OUT token OUT token OUT token IN token
NAK NAK Null data packet ACK
Status stage
IN token IN token
INT2: CTRT interrupt (control write transf er status stage shif t) Conf irm the number of by te of receiv ed data and read the receiv ed data. By the set of CCPL, transmit the Null data. Interrupt, which is occurred by control write transf er status stage shif t and by control transf er completion is dif f erent by interrupt enable setting.
(2) Continuous transmit mode (control read transfer)
Setup stage
INT1
Setup token IN token IN token
Data packet NAK NAK NAK Data packet Data packet Data packet Null data packet
ACK
INT1: CTRT interrupt (setup stage completion) Read EP0 request and conf irm the contents of request. By receiv ing SETUP token packet, response PID of EP0 is set to NAK automatically . Executes transmit data write which is requested, set transmit data length, set response PID to BUF (buf f er control), and data transmit is started.
Data stage
IN token IN token IN token IN token
ACK ACK ACK ACK
Status stage
OUT token
By the set of CCPL, ACK handshake is executed when receiv ed Null data. Interrupt which is occurred by control read transf er status stage shif t and by control transf er completion is dif f erent by interrupt enable setting.
Figure 4. Examples of abstract of control transf er operations 21
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER Device state transition
other state and to Set_Address request which Dev iceAddess is not equal to 01h to 7Fh, auto-response is not executed. M66290A manages dev ice state by H/W. To Set_Conf iguration request, auto-response is executed It manages Powered, Def ault, Address, Conf igured, to Set_Conf iguration request (Conf igurationValue is not equal and Suspended state of U SB dev ice state. to 0) which dev ice state is in Address state and to To Set_Address and Set_Conf iguration request in Set_Conf iguration request (Conf igurationValue=0) which dev ice auto-response mode, transf er can be completed state is in Conf igured state. without occurring interrupt to CPU. To Set_Address request, auto-response is executed to To other state and to Set_Conf iguration request which is dif f erent of its Conf igurationValue f rom the v alue abov e, Set_Address request (Dev iceAddess=01h to 7Fh) which dev ice state is in Def ault state, and to auto-response is not executed. Suspend detection (DVST)
Powered state
(DVSQ="000")
Suspended state
(DVSQ="100")
Resume detection (RESM) USB reset detection (DVST) USB reset detection (DVST) Suspend detection (DVST)
Def ault state
(DVSQ="001")
Suspended state
(DVSQ="101")
Resume detection (RESM) Set Address execution (DVST) (Dev iceAddress=01h to 7Fh) *Can be set to auto-response Suspend detection (DVST)
Def ault state
(DVSQ="010")
Suspended state
(DVSQ="110")
Resume detection (RESM) Set Conf iguration execution (DVST) (Conf iguration Value is not equal to 0) *Can be set to auto-response Set Conf iguration execution (DVST) (Conf iguration Value is not equal to 0) *Can be set to auto-response Suspend detection (DVST)
Def ault state
(DVSQ="011")
Suspended state
(DVSQ="111")
Resume detection (RESM)
Figure 5. Device state shift
22
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER Control transfer stage transition
M66290A manages control transf er sequence by H/W. There are setup stage, data stage, and status stage in control transf er stage, as shown in f igure 6. And when stage shif ts, CTRT interrupt occurs. There are f iv e f actors in CTRT interrupt, that is, setup stage end, control write transf er status stage shif t, control read transf er status stage shif t, control transf er end, and control transf er sequence error. And there are sev en errors as f ollows in control transf er sequence error which can be detected by H/W. If H/W detected control transf er sequence error, response PID is set to STALL("1x") automatically . 1. IN token packet receiv e in control write data stage (In token packet receiv e which did not do ACK handshake once to OUT token packet in data stage) 2. OUT token packet receiv e in control write status stage 3. OUT token packet receiv e in control read data stage. (OUT token packet receiv e which did not do data transf er once to IN token packet in data stage). 4. IN token packet receiv e in control read status stage. 5. Data packet receiv e except f or Null data in control read status stage. 6. OUT token packet receiv e in control write no data status stage. 7. Data receiv e which exceeds maximum packet size. In control write data stage, it can not be recognized as sequence error when receiv ed data packet which exceeds request wLength v alue.
Receiv e setup packet
Control transf er sequence error
Error detected
ACK transmit
(Setup stage complete)
Receiv e short packet or Receiv e IN token Control write data stage
(Control write transfer status stage transition)
ACK receiv e Control write status stage
(Control transfer complete)
Setup stage
Transmit short packet or Receiv e OUT token ACK transmit
(Setup stage complete)
ACK receiv e Control read status stage
(Control transfer complete)
Control read data stage
(Control read transfer status stage transition)
ACK transmit
(Setup stage complete)
ACK receiv e Control write no data status stage
(Control transfer complete)
Figure 6. Stage shift of control transfer
23
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (3-1) Request Register (Address : 20h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bRequest[7:0] Bit Name bRequest [7:0] bmRequest Type [7:0]
bmRequestType[7:0] Reset H/W S/W USB 00h 00h -
Bit
Name
Function
W/R
15 to 8
Request register
This fields provides bRequest of the last setup packet received.
R
7 to 0
RequestType register
This fields provides bmRequest of the last setup packet received.
R
00h
00h
-
(3-2) Value Register (Address : 22h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
wValue[15:0] Bit Name wValue [15:0] Reset H/W S/W USB 0000h -
Bit
Name
Function
W/R
15 to 0
Value register
This fields provides wValue of the last setup packet received.
R
(3-3) Index Register (Address : 24h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
wIndex[15:0] Bit Name wIndex [15:0] Reset H/W S/W USB 0000h -
Bit
Name
Function
W/R
15 to 0
Index register
This fields provides wIndex of the last setup packet received.
R
(3-4) Length Register (Address : 26h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
wLength
Bit
Bit Name wLength [15:0]
Name
Function
W/R
Reset H/W S/W USB 0000h -
15 to 0
Length register
This fields provides wLength of the last setup packet received.
R
24
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(3-5) Control Transfer Control Register (Address : 28h)
D15 CTRR Bit Name D14 D13 D12 D11 D10 D9 D8 D7 CTRW D6 D5 D4 D3 D2 D1 D0
Ctr_Rd_Buf_Nmb[5:0]
Ctr_Wr_Buf_Nmb[5:0] Reset H/W S/W USB
Bit
Name
Function
W/R
15
CTRR
Control read Control read transfer continuous transmit mode is set transfer continuous when "1" is written in this bit. transmit mode Write/Read "0" Appoint the start number of the buffer which is used in control read transfer by a unit of 64bytes.
W/R
0
-
-
14
Reserved
Ctr_Rd_ Control read buffer 13 to 8 Buf_Nmb start number [5:0]
The buffer is available from #00h to #2Fh. When control read continuous transmit mode is set, it can transmit continuously up to 255Bytes, so keep the area of the buffer of 256Bytes (4 blocks).
W/R
00h
-
-
7
CTRW
Control write When "1" is written, control write transfer continuous receive mode transfer continuous is set. receive mode Write/Read "0"
W/R
0
-
-
6
Reserved
5 to 0
Appoint the start number of the buffer which is used in control write transfer by a unit of 64bytes. Ctr_Wr_ Control write buffer The buffer is available from #00h to #2Fh. Buf_Nmb When control write continuous receive mode is set, it can receive start number [5:0] continuously up to 255bytes, so keep the area of buffer of 256bytes (4 blocks).
W/R
00h
-
-
(3-6) EP0 Packet Size Register (Address : 2Ah)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EP0_MXPS[6:0]
Bit
Bit Name
Name Write/Read "0"
Function
W/R
Reset H/W S/W USB
15 to 7 Reserved
6 to 0
EP0_MXPS [6:0]
Max Packet size
Set the maximum value of data (byte) which transmit or receive in a packet transfer. Set the value of wMaxPacketSize in request. This bit must be set after set the response PID to NAK("00").
W/R
08h
-
-
25
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(3-7) Auto-response Control Register (Address : 2Ch)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 ASCN Bit Name D0 ATAD
Bit
Name Write/Read "0"
Function
W/R
Reset H/W S/W USB
15 to 2 Reserved
1
ASCN
Set_Configuration Auto-response mode
When "1" is written into this bit, auto-response mode of Set_Configuration request is set. To the Set_Configuration request in auto-response mode, transfer can be completed without occurring interrupt to CPU. (Set of CCPL is not needed) Auto-response is done to the Set_Configuration request (ConfigurationValue is not equal to 0) in Address device state and to the Set_Configuration request (ConfigurationValue is equal to 0) in Configured state. To the other state and to the Set_Configuration request which ConfigurationVale is different from the value above, auto-response is not done. When "1" is written into this bit, automatic response mode of Set_Address request is set. To the Set_Address request in automatic response mode, transfer can be completed without occurring the interrupt to CPU. (Set of CCPL is not needed) Automatic response is done to the Set_Address request (DeviceAddress is equal to 01h to 7Fh) which device state is Default state. To the other state and to the Set_Address request which DeviceAddress is not equal to 01h to 7Fh, automatic response is not done.
W/R
0
-
-
0
ASTD
Set_Address Auto-response mode
W/R
0
-
-
(3-8) EP0_FIFO Selection Register (Address : 30h)
D15 RCNT Bit Name RCNT D14 D13 D12 D11 D10 Octl Reset H/W S/W USB 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ISEL
Bit
Name
Function If this bit is "1", every time when read EP0_FIFO register,the value of ODLN register is counted down. Write/Read "0"
W/R
15
Read count mode
W/R
14 to 11 Reserved
10
Octl
FIFO access 8 bit mode
If this bit is set to "1", data register of FIFO turns to 8-bit mode and lower 8 bit[7:0] becomes enable when access the "FIFO Data Register" of endpoint. When transmit data of odd number byte, data must be written in 8-bit mode. When read in 8-bit mode, set to 8-bit mode before data receive.
W/R
0
-
-
9-1
Reserved
Write/Read "0" 0 : Control write (OUT) buffer select 1 : Control read (IN) buffer select
0
ISEL
Buffer select
W/R
0
-
-
26
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(3-9) EP0_FIFO Control Register (Address : 32h)
D15 D14 D13 IVAL D12 BCLR D11 E0req D10 CCPL D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EP0_PID[1:0] Bit Name
ODLN[7:0] Reset H/W S/W USB
Bit
Name
Function Setting the response PID. 00 : NAK Whatever the buffer state is,do NAK handshake. 01 : BUF Response PID is selected by the state of buffer and sequence toggle bit status. (One of ACK, NAK, and DATA0/DATA1) 1x : STALL Do STALL handshake 1. When received Setup packet, turns to "00"(=NAK) automatically. 2. When received request (Set_Address, etc.) which is set to automatic response, turns to "01"(=ACK) automatically after completed the Setup transaction. 3. If sequence error occurred in control transfer,or received data in control write transfer which exceed maximum packet size, this turns to "1x"(=STALL) automatically.
W/R
15 to 14
EP0_PID [1:0]
Response PID
W/R
00
-
-
13
IVAL
In buffer status
If the control read buffer is selected, this becomes IN buffer effective state flag. When set to "1", it becomes to transmit data set state (SIE read enabled). If data is written which exceeds to the maximum byte of maximum packet size (MXPS), this bit is set to "1". When short packet transmit, set this bit to "1" after wrote transmit data. If the IVAL="1" and BCLR="1" is written at the same time, IN buffer effective state flag is set. (This is effective to transmit 0 length data) If the control readout) buffer is selected, it becomes OUT buffer effective state status. Status "1" shows that there is data which can be read. This bit shows the effective value when E0req bit is "0". If "1" is written, it is not changed. If "0" is written, flag is not changed.
W/R
0
-
-
12
BCLR
Buffer clear
If "1" is written into this bit When the selected endpoint is set to IN, IN buffer effective state flag and the data (byte) which is written are cleared. If IVAL="1" and BCLR="1" is written at the same time, data is cleared but IN buffer effective state flag is set.(This is effective to transmit 0 length data) When "1" is written into this bit, if the selected endpoint is set to OUT, OUT buffer effective state flag is cleared and read data is also cleared. When "0" is written, this bit is not changed.
W/R
0
-
-
11
E0req
EP0_FIFO ready
If this bit is "0", access to EP0_FIFO data register is enabled. And when this bit is "0", IVAL and ODLN bit shows the effective value. EP0_FIFO data register, when read or write, needs cycle time of 200ns (min). (Continuous access at 5MHz is available)
R
1
-
-
27
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
Bit Name
Name
Function
W/R
Reset H/W S/W USB
10
CCPL
Control transfer complete enable
To write "1" into this register, status stage of control transfer can be completed. If this bit is "1" and response PID is BUF("01"), Null data is transmitted in control write transfer, and do response ACK in control read transfer when received NULL data. If this bit is "0", do response NAK in status stage. This flag is reset to "0" when received setup packet.
W/R
0
-
-
9 to 8 Reserved
Write/Read "0" Received data length(byte) can be read from this register. If RCNT mode is set, every time when read EP0_FIFO data register, it is counted down by -1(8-bit mode) or by -2(16-bit mode). This bit shows effective value when E0req bit is "0".
7 to 0
ODLN [7:0]
Control write receive data length
R
00h
-
-
(3-10) EP0_FIFO Data Register (Address : 34h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EP0_FIFO[15:0] Bit Name Reset H/W S/W USB
Bit
Name
Function
W/R
15 to 0
EP0_FIFO [15:0]
EP0_FIFO data
When read, this becomes to receive data FIFO register. If it is set to 8-bit mode, lower 8 bit[7:0] is valid. When write, this becomes to transmit data FIFO register. If it is set to 8-bit mode, lower 8 bit[7:0] is valid. Both for read and write, cycle time of 200ns (min) is needed. (Continuous access at 5MHz is available) Read when IN buffer is selected or write when OUT buffer is selected is inhibited.
W/R
xxxx
-
-
(3-11) EP0 Continuous transmit Data Length (Address : 36h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDLN[7:0] Bit Name Reserved Reset H/W S/W USB
Bit 14-8
Name Write/Read "0"
Function
W/R
7 to 0
SDLN [7:0]
Set the control read continuous transmit data length (byte). It can be set up to FFh (255bytes). Control read In control read continuous transmit mode, write FIFO data (transmit data) continuous transmit after set this register. data length This is available in control read continuous transmit mode.
W/R
00h
-
-
28
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (4) Endpoint and FIFO control
Except f or EP0 f or control transf er, M66290A can set f iv e endpoints as EP1 to EP5. Each of these f iv e endpoints (EP1 to EP5) can be set to bulk, interrupt, and isochronous transf er. And y et, another constitution can conf igurated independently . Below are the constitutions to be realized. Built-in FIFO f or endpoint buf f er is 3kBy tes totally of its memory c apacity . This FIFO of 3kBy tes can div ided into each endpoint of EP0 to EP5 and to each endpoint, can assign up to 1024By tes (max) by a unit of 64By tes. Buf f er size of each endpoint must be set to ov er the capacity which is set in maximum buf f er size. In the buf f er size, which is set, by tes of m aximum packet size is used f or v alid. (If set the buf f er size to 128By tes to the endpoint which maximum packet size is set to 64By tes, 64By tes are v alid) We show setting examples to each of these buf f er of EP0 to EP5 below, and next explain about continuous transmit and receiv e f unction, FIFO control, DMA transf er, and double buf f er. To use with double buf f er constitution, 1kBy tes x2 maximum of buf f ering is realized. Continuous receiv e mode can receiv e data packet continuously up to the buf f er size which is set, or until receiv es short packet. If the data to be receiv ed is data packet of m ax packet size, it can receiv e continuously up to the buf f er size without occurring interrupt to CPU, and if the data is data packet (max packet size) which is less than buf f er size, interrupt to CPU is not occurred. In bulk transf er, when set max packet size as 64By tes, buf f er size as 1024By tes, and FIFO constitution as double buf f er, when receiv ed data of m ax packet size as 16 times (1024By tes), it became buf f er redried enable) and urge to CPU by interrupt to read receiv ed data. When receiv ed short packet, ends the continuous receiv e and buf f er became redried enable). Continuous transmit mode can transmit data packet continuously up to buf f er size which is set. Short packet transmit can be done to set IVAL f lag. And it is needed to set IVAL f lag to transmit a multiple data of m aximum packet size which is less than buf f er size. By set Null data transmit addition mode, when write a multiple data of max packet size into buf f er and transmit, Null data can be transmitted automatically af ter the last packet is transmitted .
Continuous transfer function
Continuous transf er f unction is to transmit/receiv e data which extend plural transaction without occurring interrupt to CPU. For EP1 to EP5, this f unction is ef f ectiv e when transf er ty pe is bulk transf er. In each endpoint, when continuous transf er mode is set, it can transf er data up to the buf f er size which is set to the endpoint without occurring interrupt to CPU. Construction of endpoint (EP1 to EP5) FIFO
Register Transfer type Transfer direction Double buffer (Toggle buffer) Continuous transmit/receive Buffer size EPi_TYP[1:0] EPi_DIR EPi_DBLB EP1 to EP5 Can be set to Bulk, Interrupt, isochronous transfer. Can be set to IN/OUT Can be set
Examples of endpoint FIFO setting
FIFO number 00h to 03h Memory address 000h to 0FFh Endpoint setting EP0:Control write transfer Buffer size:256Bytes Control write continuous receive mode(CTRW) FIFO area:256Bytes(4 blocks) EP0:Control read transfer Buffer size:256Bytes Control read continuous transmit mode(CTRR) FIFO area:256Bytes(4 blocks) EP2:Interrupt transfer(IN) Buffer size:64Bytes FIFO area:64Bytes(1 block) EP4:Interrupt transfer(OUT) Buffer size:64Bytes FIFO area:64Bytes(1 block) EP3:Bulk transfer(IN) Buffer size:64Bytes Double buffer constitution(DBLB) FIFO area:128Bytes(2 blocks) Not used:256Bytes(4 blocks) EP1:Bulk transfer(OUT) Buffer size:1024Bytes Double buffer constitution(DBLB) Continuous receive mode(RWMD) FIFO area:2kBytes(32 blocks)
04h to 07h
100h to 1FFh 200h to 23Fh 240h to 27Fh 280h to 2FFh 300h to 3FFh 400h to BFFh
08h EPi_RWMD Can be set (Effective in bulk transfer) Can be set (Up to 1024bytes by a unit of 64bytes) Can be set to NAK, STALL, and BUF(buffer control). Can be set Can be set Can be set ( 0 to 1023bytes) 09h
EPi_Buf_siz[3:0]
Response PID DMA transfer Receive data read and abandon mode Max packet size
EPi_PID[1:0] EPi_DMAE EPi_ACLR EPi_MXPS[9:0]
0Ah to 0Bh 0Ch to 0Fh 10h to 2Fh
29
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER FIFO control
Access to endpoint buf f er of EP0 to EP5 is done by three FIFO data registers. One is only f or EP0 and Others are common to EP1 to EP5. Common data registers are div ided into two, because accessing is dif f erent, that is f or CPU access and f or DMA transf er. Which endpoint of EP1 to EP5 to be accessed can be selected to set each FIFO selection register. Endpoint EP0 Accessing CPU access Register name EP0_FIFO data register CPU_FIFO CPU access data register DMA transf er DMA_FIFO data register
DMA transfer
To endpoint of EP1 to EP5, 16bits width or 8bit width of DMA transf er is av ailable. Each endpoint of EP1 to EP5 can be set to CPU access mode or DMA access mode by set of "EPx Conf iguration Register 1" mentioned later. DMA transf er is realized to hand shake with external DMAC and Dreq, Dack signal. Dreq is asserted when endpoint buf f er, which is set to DMA transf er mode, became ready . The means of Buf f er ready state is, if the endpoint transf er direction is set to Out (reciv e data f rom host) buf f er ready means that in read enable state, if the endpoint transf er direction is set to IN(transmit data to host) buf f er ready means that in write enable state. Setting the transf er direction can be done by "EPi Conf iguration Register 0" to each endpoint. When Dack comes f rom external DMAC af ter asserted Dreq, Dreq is negated. In DMA transf er, Dack is dealt equiv alently with CS signal and DMA_FIFO address appointment. Appoint read or write operation by RD or WR signal. This DMA transf er can be used only f or single transf er, which transf ers one word (16bit or 8bit) by one time Dreq start. In DMA transf er, as same as the CPU access, occurs endpoint buf f er not ready interrupt and endpoint buf f er empty interrupt according to endpoint buf f er state. But as to endpoint buf f er ready interrupt, it is not same as the CPU access as f ollows. In DMA transf er, endpoint buf f er ready interrupt is not occurred if the transf er direction is IN. If the transf er direction is OUT, interrupt is occurred when receiv ed short data packet and ended data transf er of all data which receiv ed in DMA transf er. Occurring of endpoint buf f er ready interrupt and to ref er DMA_DTLN, it can be known that short data packet was receiv ed. DMA_DTLN shows the number of by te of short data packet, or in the continuous receiv e mode it shows the number of by te of receiv ed data bef ore short data packet receiv e.
EP1 to EP5
Each of three FIFO registers has f unctions as f ollows. And these f unctions can be used to set "Each FIFO Selection/Control Register". Short packet transmission f unction (IVAL : IN buf f er status bit) Transmit/receiv e buf f er clear f unction (BCLR : Buf f er clear bit) Null data (data length 0) transmit f unction (IVAL & BCLR) Data length (8/16 bit) set f unction (Octl : Register 8bit mode bit) Receiv ed data length count down f unction (RCNT : Read count mode bit) *: There is none f or DMA transf er Access to CPU_FIFO data register when interrupt occurred, to know the endpoint which requested access, access the "Interrupt Status Register 0/1" and by checking the interrupt status f lag and know the endpoint which requested access, and then set endpoint to be accessed by "CPU_FIFO Selection Register". If there is no change of endpoint setting, it is not needed to set again the CPU access endpoint appointment bit.
Data transfer procedure
Data which is set to endpoint FIFO, is sent to USB bus by LSB f irst. When store the receiv ed data f rom USB bus to endpoint FIFO, it is as the same as abov e. 1 Time scale 16
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14D15
(Data send procedure to USB bus)
30
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
Double buffer operations The endpoint FIFO of EP1 to EP5 can be set to double buffer constitution. So a double of transfer data of its buffer size, which is set, can be stored.
(1) Receiv ing Below are the receiv e status examples of the endpoint which is set to double buf f er. USB side "Data1" receiv e start IN Buf f er1 data1
receiving data
Endpoint buffer status
CPU bus side Buf f er2
"Data1" receiv e end
When data receiv e ended, the buf f er is set to Ready state (read enable) and occurs INTR interrupt
Buf f er2
data receive available
Buf f er1 data1
data receive completed data read available
"Data2" receiv e start
Continuous receiv ing is av ailable bef ore data read.
IN
Buf f er2 data2
receiving data
Buf f er1 data1
data read available
"Data1" read start
IN
Buf f er2 data2
receiving data
Buf f er1 data1
reading data
OUT
Bef ore "Data1" read end "Data2" receiv e end
In OUT token receiv e to this endpoint, M66290A occurs INTN interrupt and do NAK handshake. It becomes receiv e enable af ter read of data1 ended. And occurs INTR interrupt because the buf f er is ready .
Buf f er2 data2
data receive completed data receive impossible
Buf f er1 data1
reading data
OUT
Buf f er1
data receive enable
"Data1" read end
Buf f er2 data2
data read available
Buf f er1 Af ter "Data1" read end "Data2" receiv e end M66290A Occurs INTR interrupt because the buf f er is ready .
data receive available
Buf f er2 data2
data read available
"Data3" receiv e start
IN
Buf f er1 data3
receiving data
Buf f er2 data2
data read available
data Figure 7. Double buf f er activ ities-1
: Data exists in buf f er
31
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(2) Transmitting Below are the transmit status examples of the endpoint which is set to double buf f er. USB side In token receiv e Can not transmit because the transmit buf f er is in NotReady . Request CPU to prepare transmit data by INTN interrupt Buf f er1
data transmit impossible
Endpoint buffer status
CPU bus side Buf f er2
data write available
Buf f er1 "Data1" write start
data transmit impossible
Buf f er2 data1
writing data
IN
"Data1" write end
End of data write of m aximum packet size or to set(short packet transmit) IVAL f lag, it becomes transmit data set status, and transmit becomes enable. And occurs INTR interrupt because the buf f er is in Ready (write enable). Data write is av ailable during data transmitting.
Buf f er2 data1
data transmit available
Buf f er1
data write available
"Data1" transmit start "Data2" write start
OUT
Buf f er2 data1
transmitting data
Buf f er1 data2
writing data
IN
Before "Data1" transmit end "Data2" write end
Buf f er2 End of data write of maximum packet OUT size or to set (short packet transmit) data1 IVAL flag, it becomes transmit data transmitting data set status, and transmit becomes enable. When data transmit ended, it occurs INTR interrupt because the buf f er is in Ready . Buf f er1 data2
data transmit avalable
Buf f er1 data2
data write completed data writeimpossible
IN
Buf f er2
data write avalable
"Data1" transmit end
Af ter "Data1" transmit end "Data2" write end
When data transmit ended, it occurs INTR interrupt because the buf f er is in Ready .
Buf f er1 data2
data transmit avalable
Buf f er2
data write avalable
Buf f er1 "Data3" write start data2
data transmit avalable
Buf f er2 data3
writing data
IN
data Figure 8. Double buf f er activ ities-2
: Data exists in buf f er
32
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(4-1) CPU_FIFO Selection Register (Address : 40h)
D15 RCNT Bit Name RCNT D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CPU_EP[3:0] Reset H/W S/W USB 0 -
Bit
Name
Function If this bit is "1", every time when read CPU_FIFO register, CPU_DTLN register value is counted down. Write/Read "0" Appoint the CPU access endpoint. "0001"=EP1,"0010"=EP2,"0011"=EP3, "0100"=EP4,"0101"=EP5 EP0 can not be appointed.
W/R
15
Read count mode
W/R
14 to 4 Reserved
3 to 0
CPU_EP [3:0]
CPU access endpoint
Don't change the setting in writing (IN) or in reading (OUT). Change of the setting of the endpoint of direction IN must be done after confirmed that IVAL="0" and Creq="0", or IVAL="1" and Creq="1". Change of the setting of the endpoint of direction OUT must be done after confirmed that IVAL="1" and Creq="0", or IVAL="0" and Creq="1".
W/R 0000
-
-
(4-2) CPU_FIFO Control Register (Address : 42h)
D15 D14 D13 IVAL D12 BCLR D11 Creq D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CPU_DTLN[10:0]
Bit
Bit Name
Name Write/Read "0"
Function
W/R
Reset H/W S/W USB
15, 14 Reserved
13
IVAL
IN buffer status
If the selected endpoint is set to IN, this becomes IN buffer effective state flag. When set to "1", it becomes transmit data set state. (SIE is available to read) When the data (byte) which exceeds to the maximum packet size (MXPS) is written, this bit is set to "1". In short packet transmit, set this bit to "1" after wrote the transmit data. If IVAL="1" and BCLR="1" is written at the same time, the effective state flag is set. (This is effective to transmit 0 length data) If the selected endpoint is set to OUT, it becomes to OUT buffer effective state status. Status "1" shows that there is data which is available to read. When Creq bit is "0", this bit shows effective value. This bit is not changed when "1" is written. Flag is not changed when "0" is written.
W/R
0
-
-
33
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
Bit Name
Name
Function
W/R
Reset H/W S/W USB
If the selected endpoint is set to IN, when "1" is written into this bit, the IN buffer effective state flag and the data (byte) which is written are cleared. If IVAL="1" and BCLR="1" is written at the same time, data is cleared but the IN buffer effective state flag is set. (This is effective to transmit 0 length data) If the selected endpoint is set to OUT, when "1" is written into this bit, the OUT buffer effective state flag and the read data (byte) are cleared. If it is set to double buffer, the state of write/read enable buffer for CPU is cleared. To set the EPi_ACLR, USB bus buffer is cleared. This bit is not changed when "0" is written.
12
BCLR
Buffer clear
W/R
0
-
-
If this bit is "0", access to CPU_FIFO data register is available. And if this bit is "0", the bit of IVAL and CPU_DTLN bit shows the effective value. When read or write to CPU_FIFO register, 200ns (min) of cycle time is needed. (Continuous access at 5MHz is available) If the access end point is changed, 200ns (min) of recovery time is needed.
11
Creq
CPU_FIFO ready
R
1
-
-
10 to 0
CPU_DTL N[10:0]
CPU_FIFO receive data length
When read this register, receive data length (byte) appears. When RCNT mode is set, every time when read CPU_FIFO register, it is counted down by -1 (8-bit mode) or by -2 (16-bit mode). If RCNT mode is not set, this register turns to 000h after all of received data is read. This bit shows effective value when Creq bit is "0".
R
000h
-
-
34
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(4-3) CPU_FIFO Data Register (Address : 44h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CPU_FIFO[15:0] Reset H/W S/W USB
Bit
Bit Name
Name
Function
W/R
15 to 0
CPU_FIFO CPU_FIFO data [15:0]
If the selected endpoint is set to OUT, this becomes to receive data FIFO register. If the selected endpoint is set to IN, this becomes to transmit data FIFO register. If the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] is valid. When read or write, 200ns (min) of cycle time is needed. (Continuous access at 5MHz is available) Read operation when direction IN is appointed or write operation when direction OUT is appointed, write operation is inhibited.
W/R
xxxx
-
-
(4-4) DMA_FIFO Selection Register (Address : 48h)
D15 MODE Bit Name D14 D13 D12 D11 D10 D9 D8
DMAEN
D7
D6
D5
D4
D3
D2
D1
D0
DMA_EP[3:0] Reset
Bit
Name
Function Set the operation mode of DMA transfer. 0 : High speed transfer mode 1 : One word transfer mode In high speed transfer mode, when endpoint buffer is in read/write enable in the state that DMA transfer enable, Dreq is asserted. In one word transfer mode, when endpoint buffer is in read/write enable in the state that DMA transfer enable and Dack="H", Dreq is asserted. In both mode, Dreq detects Dack="L" and is negated. Write/Read "0" If this bit is "1", endpoint buffer which is appointed by DMA_EP[3:0] is enable to write or when read is enable, Dreq is asserted. If "0" is written in DMA transferring, DMA transfer is forced to end. Write/Read "0" Appoint the endpoint for DMA transfer. "0001"=EP1,"0010"=EP2,"0011"=EP3, "0100"=EP4,"0101"=EP5 EP0 can not be appointed. Don't change the setting during write (IN) or read (OUT). Change of the setting of the endpoint of direction IN must be done after confirmed that IVAL="0" and Dreq="0", or IVAL="1" and Dreq="1". Change of the setting of the endpoint of direction OUT must be done after confirmed that IVAL="0" and Dreq="1".
W/R
H/W S/W USB
15
MODE
DMA operation mode
W/R
0
-
-
14 to 9 Reserved
8
DMAEN
DMA transfer enable
W/R
0
-
-
7 to 4 Reserved
3 to 0
DMA_EP [3:0]
DMA transfer endpoint
W/R 0000
-
-
35
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(4-5) DMA_FIFO Control Register (Address : 4Ah)
D15 D14 D13 IVAL Bit Name D12 BCLR D11 Dreq D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DMA_DTLN[10:0] Reset H/W S/W USB
Bit
Name Write/Read "0"
Function
W/R
15, 14 Reserved
13
IVAL
IN buffer status
If the selected endpoint is set to IN, this becomes IN buffer effective state flag. When set to "1", it becomes transmit data set state. (SIE is available to read) When the data (byte) which exceeds to the maximum packet size (MXPS) is written, this bit is set to "1". In short packet transmit, set this bit to "1" after wrote the transmit data. If IVAL="1" and BCLR="1" is written at the same time, the IN buffer effective state flag is set to "1". (This is effective to transmit 0 length data) If the selected endpoint is set to OUT, it becomes to OUT buffer effective state status. Status "1" shows that there is data which is available to read. When Creq bit is "0", the value of this bit is effective. This bit is not changed when "1" is written. Flag is not changed when "0" is written.
W/R
0
-
-
If "1" is written into this bit when the selected endpoint is set to IN, IN buffer effective state flag and the data (byte) which is written are cleared. If the IVAL="1" and BCLR="1" is written at the same time, the data is cleared but the IN buffer effective state flag is set.(This is effective to transmit 0 length data) If "1" is written into this bit when the selected endpoint is set to OUT, OUT buffer effective state flag and the read data (byte) are cleared. If it is set to double buffer, the state of buffer which can be read or write for CPU bus is cleared. To set the EPi_ACLR, USB bus buffer is cleared. This bit is not changed when "0" is written.
12
BCLR
Buffer clear
W/R
0
-
-
36
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
Bit Name
Name
Function
W/R
Reset H/W S/W USB
11
Dreq
DMA_FIFO ready
If this bit is "0", then access is available to DMA_FIFO register. And if this bit is "0", then the bit of IVAL and DMA_DTLN is valid. This bit is used as DMA request signal (Dreq).
R
1
-
-
10 to 0
DMA_DT LN[10:0]
DMA_FIFO receive data length
When read this register, receive data length (byte) is appears. This bit is valid when Dreq bit is "0".
R
000h
-
-
(4-6) DMA_FIFO Data Register (Address : 4Ch)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DMA_FIFO[15:0] Bit Name Reset H/W S/W USB
Bit
Name
Function
W/R
15 to 0
DMA_FI FO[15:0]
DMA_FIFO data
If the selected endpoint is set to OUT, this becomes to receive data FIFO register. If the selected endpoint is set to IN, this becomes to transmit data FIFO register. If the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] are valid. Read operation when the endpoint appointed direction IN, or write operation when the endpoint appointed direction OUT, is inhibited.
W/R
xxxx
-
-
37
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(4-7) EPi Configuration Register 0 ( i=1 to 5) (Address : EP1=60h, EP2=64h, EP3=68h, EP4=6Ch, EP5=70h)
D15 D14 D13 DIR D12 ITMD D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EPi_TYP[1:0]
EPi_Buf_siz[3:0]
DBLB RWMD
EPi_Buf_Nmb[5:0]
The EPi configuration register 0 must be set in a state of response PID is NAK("00"). Bit Bit Name Name Function To set the transfer type of endpoint. 00 : not Configured 01 : bulk transfer 10 : interrupt transfer 11 : isochronous transfer To set the transfer direction of endpoint 0 : OUT (receive data from host) 1 : IN (transmit data to host) When changed the state of transfer direction, clear (EPi_ACLR) the endpoint buffer. To set the sequence toggle bit mode of interrupt transfer. 0 : Alternation data toggle bit mode (Only toggled when transfer completed with no problem) 1 : Continuous toggle bit mode (Whatever the hand shake exists or the types are, it toggles every time when data packet is transmitted ) This is effective when endpoint is set to interrupt(IN) transfer. Set endpoint buffer size at a unit of 64Bytes. "0000"=64Bytes, "0001"=128Bytes, ...., "1110"=960Bytes, "1111"=1024Bytes Set the constitution of endpoint buffer. 0 : Single buffer mode 1 : Double buffer mode In double buffer mode, double of the buffer size is taken as the endpoint buffer. If "1" is written into this bit, continuous transfer mode of endpoint is set. When the direction of endpoint is set to OUT, then it is set to continuous receive mode. And when the direction of endpoint is set to IN, then it is set to continuous transmit mode. Continuous receive mode can receive data packet up to the buffer size which is set, or can receive continuously before receives short packet. Continuous transmit mode can transmit data packet up to the buffer size which is set, and transmission of short packet can be done by set the IVAL flag. In data packet (max packet size) receive which is less than buffer size, interrupt to CPU does not occur. Continuous transfer mode is effective only in bulk transfer. W/R Reset H/W S/W USB
15 to 14
EPi_TYP [1:0]
Transfer type
W/R
00
-
-
13
EPi_DIR
Transfer direction
W/R
0
-
-
12
EPi_ITMD
Interrupt toggle mode
W/R
0
-
-
11 to 8
EPi_Buf_ siz[3:0]
Buffer size
W/R 0000
-
-
7
EPi_DBLB Double buffer mode
W/R
0
-
-
6
EPi_ RWMD
Continuous transfer mode (only for Bulk transfer)
W/R
0
-
-
5 to 0
EPi_Buf_ Buffer start number Nmb[5:0]
Appoint the first number of the buffer of a unit of 64Bytes. Buffer exists from #00h to #2Fh. Buffer size(double of the buffer size in double buffer mode), which is appointed from the first, is secured for endpoint buffer. Set that plural of endpoint do not occupy the same buffer area.
W/R
00h
-
-
38
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(4-8) EPi Configuration Register 1 ( i=1 to 5 ) (Address : EP1=62h, EP2=66h, EP3=6Ah, EP4=6Eh, EP5=72h)
D15 D14 D13 D12 D11 ACLR D10 Octl D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EPi_PID[1:0]
DMAMD NULMD
EPi_MXPS[9:0]
The EPi configuration register 1 must be set in a state of response PID is NAK("00"). Bit Bit Name Name Function Set response PID. 00 : NAK Whatever the buffer state is, do NAK handshake. 01 : BUF Response PID is selected according to the state of buffer and sequence toggle bit. (In bulk/interrupt transfer, one of ACK, NAK, DATA0, and DATA1) 1x : STALL Do STALL handshake. If the transfer direction of selected endpoint is OUT, when received data which exceeded maximum packet size (MXPS), it becomes "1x" (=STALL) automatically. W/R Reset H/W S/W USB
15, 14
EPi_ PID [1:0]
Response PID
W/R
00
-
-
13
Set the access mode to endpoint buffer. EPi_ DMA transfer mode 0 : CPU access mode DMAMD 1 : DMA transfer mode To set this bit as "1", Null data addition transmit mode is set . In the endpoint which is set to continuous transmit mode, when write a multiple data of maximum packet size into buffer and transmit, Null data is transmitted automatically after transmitted the last packet. This setting is effective when continuous transmit mode is set.
W/R
0
-
-
12
EPi_ NULMD
Null data addition transmit mode
W/R
0
-
-
11
EPi_ ACLR
OUT buffer automatic clear mode
When the selected endpoint is set to OUT and if this bit is set to "1", OUT buffer effective flag and read data (number of byte) is cleared. In this state(OUT buffer does not become effective state), SIE side writes data from host into OUT buffer but CPU side does not read. When set this bit to "1", whatever the transfer direction is, endpoint buffer (all buffer of single/double buffer) are cleared. When clear the endpoint buffer, set this bit to "1" and then set again to "0".
W/R
0
-
-
10
EPi_Octl
FIFO access 8 bit mode
When this bit is set to "1", FIFO data register becomes 8-bit mode and when accessed "FIFO Data Register" of endpoint, lower 8bit[7:0] becomes effective. When transmit odd number of byte, it is needed to write in 8-bit mode. When read in 8-bit mode, set to 8-bit mode before data receive.
W/R
0
-
-
9 to 0
EPi_ MXPS [9:0]
Max Packet size
Set the maximum data size (Byte) to transmit/receive in one packet transfer. Set the value of wMaxPacketSize in request.
W/R 040h
-
-
39
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Storage temperature Ratings -0.3 to +4.2 -0.3 to VCC+0.3 -0.3 to VCC+0.3 20 400 -55 to +150 Unit V V V mA mW C
RECOMMENDED OPERATING CONDITIONS
Limits Symbol VCC GND VI VI(Vbus) VO Topr Parameter Min. Supply voltage Supply voltage Input voltage Input voltage ( Only for Vbus Input ) Output voltage Operating temperature Normal input tr, tf Input rise, fall time Schmidt trigger input 5 ms 0 0 0 0 +25 3.0 Typ. 3.3 0 VCC 5.25 VCC +70 500 Max. 3.6 V V V V V C ns Unit
40
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER ELECTRICAL CHARACTERISTICS
Limits Symbol VIH VIL VT+ VTVOH VOL VOH VOL VOH VOL IIH IIL IOZH IOZL Rdv Rdt Ru ICC(A) Parameter "H" input voltage Xin "L" input voltage Threshold voltage in positive direction
Note 1
Condition Min. VCC = 3.6V VCC = 3.0V VCC = 3.3V 0.5 IOH = -50uA Xout VCC = 3.0V IOL = 50uA IOH = -2mA
Note 2
Unit Typ. Max. 3.6 0.9 2.4 1.65 V V V V V 0.4 2.6 0.4 2.6 0.4 10 -10 10 -10 100 50 50 V V V V V uA uA uA uA k k k 55 mA 2.52 0 1.4
Threshold voltage in negative direction "H" output voltage "L" output voltage "H" output voltage VCC = 3.0V IOL = 2mA IOH = -4mA
Note 3
2.6
"L" output voltage "H" output voltage VCC = 3.0V "L" output voltage "H" input current VCC = 3.6V "L" input current "H" output current in off status "L" output current in off status Pull down resistance Pull down resistance Pull up resistance Average supply current in operation mode
D15-0 ,TDO Note 4 Note 5 Note 6
IOL = 4mA VI = VCC VI = GND VO = VCC VCC = 3.6V VO = GND
f(Xin)=48MHz,VCC = 3.6V USB transmit state Oscillator disable,PLL disable, USB transceiver enable, TrON=H/L output VI=Vcc or GND fixed,Vcc = 3.6V Oscillator disable,PLL disable, USB transceiver disable, TrON=H/L output VI=Vcc or GND fixed,Vcc = 3.6V Suspend state Oscillator disable,PLL disable, USB transceiver disable, TrON=H/L output VI=Vcc or GND fixed,Vcc = 3.6V H/W reset state
40
2
4
mA
ICC(S)
Supply current in static mode
30
200
uA
10
100
uA
Notes 1: All input and bidirection pins except for Xin (except for USB buffer) 2: INT,Dreq,TDO output pins 3: D15-0 input /output pins 4: Vbus input pins 5: TEST1,TEST2,TCK input pins 6: TRST,TMS,TDI input pins
41
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER ELECTRICAL CHARACTERISTICS (USB) (1) DC CHARACTERISTICS
Limits Symbol
VDI VCM VSE VOL VOH IOZL IOZH Ro(Pch) Ro(Nch)
Parameter
Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold "L" Output voltage VCC = 3.0V "H" Output voltage "L" output current in off status VCC = 3.6V "H" output current in off status Output resistance VCC = 3.3V Output resistance
Test condition Min.
| (D+)-(D-) | 0.2 0.8 0.8 RL of 1.5K to 3.6V RL of 15K to GND VO =0V VO =3.6V VO =0V VO =3.3V 2.8 -10 -10 4 4 7 7 2.5 2.0 0.3 3.6 10 10 15 15
Unit Ty p. Max.
V V V V V mA mA
(2) AC CHARACTERISTICS
Limits Symbol
tr tf TRFM VCRS
Parameter
Rise transition time Fall transition time Rise/fall time matching Output signal crossover voltage
Test condition Min.
10% to 90% of the data signal 10% to 90% of the data signal tr/tf CL=50pF CL=50pF CL=50pF 4 4 90 1.3
Unit Ty p. Max.
20 20 110 2.0 ns ns % V
42
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
SWITCHING CHARACTERISTICS
Symbol
ta(A) ta(CTRL) tv(CTRL) ten(CTRL) tdis(CTRL) td(Dacktd(WR-INT ) twh(INT ) twh(Dreq) td(CTRLDreq) td(DackhDreq) td(TCKTDOV) td(TCKTDOX)
Parameter
Address access time Control access time Data valid time after control Data output enable time after control Data output disable time after control Dreq disable propagation time INT disable propagation time INT "H" pulse width Dreq "H" pulse width Dreq output enable time after control Dreq output enable time after Dack TDO output enable time after TCK TDO output disable time after TCK
Test condition
Limits Min. Typ. Max. 30 30 0 0 0 20 20 60
Unit
ns ns ns ns ns ns ns ns ns ns ns
CL=50pF 320 60 60 20
60
30 30
ns ns
TIMING REQUIREMENTS
Symbol
tsu(A) th(A) tw(CTRL) trec(CTRL) tsu(D) th(D) tw(cycle) tw(RST ) tst(RST ) tc(TCK) tw(TCKH) tw(TCKL) tsu(TDI-TCK) th(TDI-TCK) tw(TRST) td(CTRLDack)
Parameter
Address setup time Address hold time Control pulse width Control recovery time Data setup time Data hold time FIFO access cycle time RESET pulse width Control start time after RESET TCK cycle time TCK "H" pulse width TCK "L" pulse width TDI,TMS setup time TDI,TMS setup time TRST "L" pulse width TRST "L" pulse width
Test condition
Limits Min. 30 0 30 30 20 0 200 100 100 100 40 40 20 20 100 83 Typ. Max.
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
43
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER Measurement circuit
1. Terminals except f or USB buf f er block Vcc Input Vcc RL=1kohm SW1 D15-0, TDO CL SW2 RL=1kohm Other output CL Item tdis(CTRL(LZ)) tdis(CTRL(HZ)) ta(CTRL(ZL)) ta(CTRL(ZH)) SW1 close open close open SW2 open close open close
P.G
DUT
50ohm
(1) Input pulse lev el : 0 to 3.3V Input pulse rise/f all time : tr=tf =3ns Input timing v oltage : 1.65V Output timing v oltage : Vcc/2 (tdis(LZ) is measured at 10% of output, tdis(HZ) is measured at 90% of output) (2) Capacitance CL includes stray capacitance and probe capacitance.
2. USB buf f er block
Vcc
Vcc RL=1.5kohm D+ RL=27ohm CL RL=15kohm (1) tr, tf is measured f rom 10% to 90% of output. (2) Capacitance CL includes stray capacitance and probe capacitance. CL
DUT
DRL=27ohm RL=15kohm
GND
44
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
TIMING DIAGRAM
(1) Write timing
tsu(A) th(A)
A6 to 1
Address is established
tw(cycle) trec(CTRL)
tw(CTRL)
CS ,WR
(note 2) tsu(D) th(D)
D15 to 0
Data input is established
(2) Read timing
ta(A) th(A)
A6 to 1
Address is established
tw(cycle) ta(CTRL) trec(CTRL) tw(CTRL) (note 1)
CS ,RD
(note 3) tv(CTRL) ten(CTRL) tdis(CTRL)
D15 to 0
Data output is established
note 1 : tw(cycle) is needed when access FIFO. note 2 : Write is done in the overlap period when CS and WR is active "L". Spec from the positive edge is valid from the fastest inactive signal. Spec of pulse width is valid of the overlap period of active "L". note 3 : Read is done in the overlap period of CS and RD is active "L" Spec from the negative edge is valid from the latest signal. Spec from the positive edge is valid form the fastest inactive signal. Spec of pulse width is valid during active "L" overlap period.
45
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (3) DMA Transfer Timing -1 In case of Full speed transfer mode (DMA operation mode register : MODE=0) (3-1) Write timing -1
twh(Dreq)
Dreq (note 4)
td(CTRL-Dreq) td(Dack-Dreq)
Dack
tw(CTRL)
trec(CTRL)
WR
(note 5)
tsu(D) th(D)
D15 to 0
Data input is established
(3-2) Read timing -1
twh(Dreq)
Dreq (note 4)
td(Dack-Dreq)
td(CTRL-Dreq)
Dack
ta(CTRL) tw(CTRL)
trec(CTRL)
RD (note 6)
tv(CTRL) ten(CTRL) tdis(CTRL)
D15 to 0
Data output is established
note 4 : Inactive condition of Dreq is Dack="L" And when next DMA transfer exists, spec when Dreq turns to active is valid the latest one of twh(Dreq) or td(CTRL-Dreq). note 5 : Write is done in the overlap period when Dack and WR is active "L". Spec from the positive edge is valid from the fastest inactive signal. Spec of pulse width is valid of the overlap period of active "L". note 6 : Read is done in the overlap period of Dack and RD is active "L" Spec from the negative edge is valid from the latest signal. Spec from the positive edge is valid form the fastest inactive signal. Spec of pulse width is valid during active "L" overlap period.
46
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(3-3) Write timing -2
Dreq (note 4)
td(CTRL-Dreq)
td(CTRL-Dreq)
Dack
td(Dack-Dreq)
RD
tw(CTRL)
tw(CTRL)
WR
(note 5)
tsu(D) th(D) tsu(D) th(D)
D15 to 0
(3-4) Read timing -2
Dreq (note 4)
td(CTRL-Dreq) td(CTRL-Dreq)
Dack
td(Dack-Dreq)
tw(CTRL)
tw(CTRL)
RD
(note 6)
WR
ta(CTRL) tv(CTRL) ta(CTRL) tv(CTRL)
D15 to 0
note 4 : Inactive condition of Dreq is Dack="L" And when next DMA transfer exists, spec when Dreq turns to active is valid the latest one of twh(Dreq) or td(CTRL-Dreq). note 5 : Write is done in the overlap period when Dack and WR is active "L". Spec from the positive edge is valid from the fastest inactive signal. Spec of pulse width is valid of the overlap period of active "L". note 6 : Read is done in the overlap period of Dack and RD is active "L" Spec from the negative edge is valid from the latest signal. Spec from the positive edge is valid form the fastest inactive signal. Spec of pulse width is valid during active "L" overlap period.
47
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER (4) DMA Transfer Timing -2 In case of one word transfer mode (DMA operation mode register : MODE=1) (4-1) Write timing -1
twh(Dreq)
Dreq (note 7)
td(Dack-Dreq)
td(Dackh-Dreq)
Dack
td(CTRL-Dack) trec(CTRL)
tw(CTRL)
WR
(note 5)
tsu(D) th(D)
D15 to 0
Data input is established
(4-2) Read timing -1
twh(Dreq)
Dreq (note 7)
td(Dack-Dreq)
td(Dackh-Dreq)
Dack
td(CTRL-Dack) ta(CTRL) tw(CTRL)
trec(CTRL)
RD (note 6)
tv(CTRL) ten(CTRL) tdis(CTRL)
D15 to 0
Data output is established
note 7 : Inactive condition of Dreq is Dack="L" And when next DMA transfer exists, spec when Dreq turns to active is valid the latest one of twh(Dreq) or td(Dackh-Dreq). note 5 : Write is done in the overlap period when Dack and WR is active "L". Spec from the positive edge is valid from the fastest inactive signal. Spec of pulse width is valid of the overlap period of active "L". note 6 : Read is done in the overlap period of Dack and RD is active "L" Spec from the negative edge is valid from the latest signal. Spec from the positive edge is valid form the fastest inactive signal. Spec of pulse width is valid during active "L" overlap period.
48
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(5) Interrupt timing
twh(INT)
INT
td(CTRL-INT)
CS ,WR
(note 8)
note 8 : Write is done in the overlap period when CS and WR is active "L". Spec from the positive edge is valid from the fastest inactive signal.
(6) Reset timing
tw(RST)
RST,TRST
tst(RST)
CS ,WR
49
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER
(7) JTAG timing
tc(TCK) tw(TCKL) tw(TCKH)
TCK
tsu(TDI-TCK)
th(TCK-TDI)
TDI,TMS
td(TCK-TDOV)
td(TCK-TDOX)
TDO
tw(TRST)
TRST
50
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER Abstraction of JTAG
M66290A has JTAG (Joint Test Action Group) interf ace which meets IEEE 1149.1 test access port spec. This JTAG interf ace can be used f or input/output path (boundary scan path) f or boundary scan test. Further inf ormation as to JTAG test access port, ref er to "IEEE Std. 1149.1a-1993". Test mode input (TMS) Test mode select input to control status shif t of test circuit. This is sampled by the positiv e edge of TCK. Test reset input (TRST) "L" activ e test reset input to initialize the test circuit asy nchronously . To assure this reset f unction, keep TMS input as "H" when this signal changes f rom "L" to "H".
Pin descriptions
Pin description which relates to JTAG interf ace of M66290A are as f ollows. Test clock input (TCK) Clock input into test circuit. Test data input (TDI) Sy nchronous serial input to input test command code and test data. Data is sampled by the positiv e edge of TCK. Test data output (TDO) Sy nchronous serial output to output test command code and test data. Output data changes by the negativ e edge of TCK and is output only in the state of Shif t-IR or Shif t-DR. In other state,keeps "Z".
JTAG circuit constitution
JTAG circuit of M66290A is constituted by the blocks as f ollows. (1) Command register which keeps command code which is f etched through the boundary scan path. (2) Data register group which is accessed through the boundary scan pass. (3) Test access port (TAP) controller to control the status shif t of JTAG block. (4) Control logic f or input select, output select, and so.
M66290A
Data register group TDI 11 Boundary scan register (JTAGBSR) By pass register (JTAGBPR) ID code register (JTAGIDR) Decoder 12 TDO Command register (3bits) (JTAGIR) TMS 10 TCK 9 TAP controller
TRST 8
51
MITSUBISHI
M66290AGP/FP
USB DEVICE CONTROLLER Abstract of JTAG operations
There are f our basic access to command register and to data register. And the access is executed based on the status shif t of TAP controller. TAP controller is shif ted of its status by the TMS input and make a control signal which is needed to each state. Capture operation Result of the boundary scan test or the f ixed data which is def ined to each register, is sampled. For operation, load the input data into shif t register stage. Shif t operation Through the boundary scan path, access f rom external is done. M66290A set the data f rom external and at the same time, output the data which is sampled by capture operation. For register operation, right shif t is executed among shif t register stage of each bit. Update operation In shif t operation, driv e the data which is set by external. For register operation, transf er the v alue which is set to shif t register stage, to parallel output stage.
Input select Data input Shift register stage To next cell Data output
JTAG interf ace shif ts the internal state according to TMS input, and do two kinds of operations as f ollows. Both are basically executed in turn of "Capture -> Shif t -> Update". IR path sequence Set the command code into command register and when path sequence comes, select the data register which is the object of the operation. DR path sequence To selected data register, ref er or set the data.
A Y A/B D T Q D T Q
From previous cell B Shift-DR/IR Clock-DR/IR Update-DR/IR Test reset
Parallel output stage
Figure. Basic construction of JTAG related register
1
Test-Logic-Reset 0 1 1 Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 Update-IR 0 Exit2-IR 1 Exit2-IR 1 0 0 Exit1-IR 0 Pause-IR 1 0 1 Capture-IR 0 0 Shift-IR 1 0 Select-IR-Scan 0 1
0
Run-Test-/Idle
note: 0,1 shows the status of TMS input signal Figure. Status shif t of TAP controller 52

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